Metal-oxide-semiconductor (MOS) transistors are the primary building blocks for modern integrated circuits. A typical highly integrated circuit, such as a microelectronic device, can contain millions of transistors on a single silicon substrate no bigger than a thumbnail. Generally, a transistor, or device, hereinafter referred to interchangeably, includes a gate structure formed on a substrate with a source region and a drain region, separated from each other by the gate structure and formed within the substrate, adjacent to the gate structure. A transistor may be thought of as an electronic switch having three nodes. When a voltage is applied to a first node of the transistor, i.e., the gate, the flow of electric current between the other two nodes, i.e., the source and the drain regions, via a channel region in the substrate below the gate, is modulated. For example, to turn one type of n-channel (NMOS) transistor “ON,” a positive voltage is applied to the gate, allowing electrical current to flow between the source and drain. To turn this transistor “OFF,” zero volts is applied to the gate which cuts off the flow of electrical current between the source and drain.
Process induced strain (sometimes referred to as stress) can greatly enhance the carrier mobility in short channel devices in conventional planar transistor devices. For example, in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), a conformal silicon nitride-capping layer (Si3N4) can be deposited on the transistor structure to induce tensile uniaxial strain resulting in electron mobility enhancement. In p-type MOSFETs, selective epitaxial deposition of Si1-xGex can be introduced into the source/drain regions to create longitudinal compressive strain resulting in hole mobility enhancement.
A recent development in semiconductor processing is the non-planar transistor, or multi-gate transistor or tri-gate transistor. A tri-gate transistor includes a thin semiconductor body (e.g., a silicon fin) formed on a substrate and having a top-surface and two sidewall surfaces perpendicular to the top surface. A gate structure is formed on the substrate and the silicon fin, perpendicular to the silicon fin. Source and drain regions are formed in the fin on opposite sides of the gate structure. Because the gate structure surrounds the silicon fin on the three surfaces, the transistor essentially has three gates controlling the current through the fin or channel region. These three gates provide three channels for electrical signals to travel, thus effectively increasing the conductivity per unit surface area as compared to a conventional planar transistor.
Tri-gate transistors generally have superior performance to bulk gate devices. This is due to the proximity of the top and side gates relative to one another which causes full depletion and results in steeper sub-threshold current swing (SS) and smaller drain induced barrier lowering (DIBL). The SS and DIBL typically are used to determine short-channel effects (SCEs) in a transistor. In general, it is desired that SCEs are low such that the transistor off-state leakage current, IOFF (i.e., a current flowing between source and drain regions when a transistor is in an OFF state), remains as low as possible. A steeper SS and/or reduced DIBL indicates lower IOFF, and thus smaller and typically better SCEs.